Why Cerebras builds an AI processor the size of a wafer

Cerebras builds an AI processor across an enormous square of silicon. Its WSE-3 measures 46,225 square millimetres: a square 21.5 centimetres on each side, calculated from the published area. Making a processor that large creates a different engineering problem. The design must keep working even when some microscopic parts of that expanse are imperfect.[1]

The reason to attempt it is data movement. A wafer-scale processor puts many computing units beside their own fast memory, linked across the silicon. Researchers describe a distributed machine inside the processor: software must decide where to place information and how the units cooperate.[2]

This is also a publicly listed business supplying both equipment and cloud services. Cerebras shares began trading on Nasdaq under CBRS on 14 May 2026, and the company announced the closing of its initial public offering the following day. Its unusual processor is the foundation for several ways of selling AI computing.[3]

A defect need not ruin the whole processor

Cerebras’s explanation of the WSE-3 describes 970,000 physical cores, with 900,000 active in the shipping product. Spare cores give the system room to accommodate faults. Redundant communication paths let it route around damaged locations while preserving the connected arrangement used by software. The design therefore anticipates imperfections during manufacture. These core counts are not a factory yield percentage: the company also acknowledges that clustered defects can overwhelm the available redundancy. The engineering achievement is making defects manageable at a very large scale.[1]

Fast local memory changes the software problem

The total memory consists of many small local stores. As the USENIX authors explain, reaching across the mesh requires passing through intermediate routers. Software divides weights and intermediate values into pieces that fit locally, then schedules their movement. Aggregate bandwidth adds many local connections together; it does not give every core equally fast access to all memory.[2]

Large models can also span multiple wafers. Cerebras’s May account of enterprise trials with Kimi K2.6 describes distributing the model’s stored weights across the hardware and streaming intermediate activations between wafers. Activations are values produced during the computation and passed to later stages. In that implementation, the stored weights use four bits each while arithmetic uses 16-bit floating point. The distinction helps explain the design: compact storage and the precision used during computation are separate choices.[4]

A model with more weights consequently needs an arrangement of machines that can hold and process them. The wafer-scale approach changes the size and internal organisation of each building block; the multi-wafer example shows how the surrounding system remains part of the product. Model placement, communication and serving software still determine how effectively those blocks work together.[4]

CS-4 combines three wafers in a new system

The CS-4, introduced in August 2026, uses three WSE-3 Turbo processors. Each has 44GB of integrated SRAM and a company-specified 250 petaflops of AI compute. SRAM is the fast local memory built into the processor. The system total therefore describes three processors working together.[5]

The sixfold increase in peak compute combines three times as many wafers with twice the advertised compute per wafer. It is a system-specification comparison, not evidence that an application finishes six times faster.[5]

The physical assembly changes too. A modular unit around each wafer brings together power conversion, liquid cooling, data connections and control electronics. Separating it from the power supplies is intended to simplify manufacturing and upgrades. Packaging and serviceability matter when an unusual chip becomes equipment for a data centre.[5]

The processor can work alongside other suppliers’ chips

In July, AMD and Cerebras announced a combined system using AMD Helios hardware to process prompts and Cerebras hardware to generate responses. Their performance claim needs its full denominator: up to five times the tokens per second per watt came from supplier modelling for the trillion-parameter Kimi K2.6 model, at comparable interactivity, against a Cerebras wafer-only configuration. It was not a measured fivefold advantage over an Nvidia deployment. The announcement illustrates a commercial role for complementary hardware, with each supplier addressing part of the work.[6]

An AWS design described by Cerebras follows a related division. AWS Trainium processes the prompt, then transfers the model’s accumulated attention state over AWS networking to Cerebras for generation. That transfer connects the two stages so generation can continue from the processed prompt. The arrangement makes the network and the hand-off part of the engineering proposition, alongside the processors.[7]

The schedules remain dated expectations: in its August financial update, Cerebras anticipated production of the AMD combination in the fourth quarter of 2026 and availability through Amazon Bedrock in the first quarter of 2027. Those statements describe planned delivery, rather than proving either service was already available when announced.[8]

Cloud services are already a substantial business

For the quarter ended 30 June 2026, Cerebras reported $180.110 million of GAAP revenue: $54.119 million from hardware and $125.991 million from Cloud and Other Services. The latter was approximately 70% of the total, calculated from those reported categories. It includes more than pure inference fees, including reported pass-through revenue. The figures show that selling access and services around the hardware was already a substantial activity alongside selling equipment.[8]

The architecture creates distinctive engineering choices. Keeping data close to computing can reduce communication, while a huge mesh requires careful placement and scheduling. The useful question is how a complete system organises the work of the model it will run.[2]

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