Most chips spread their important components across a flat neighbourhood. The farther data must travel between memory and logic, the more time and energy the journey consumes. Monolithic three-dimensional integration tries a different geometry: build useful devices above one another and connect the floors with short vertical links.
A Purdue-led team reports wafer-scale integration of more than 100,000 atomic-layer-deposited indium-oxide devices on 200-millimetre silicon wafers. The fabricated stack contained three functional tiers. The measured device characteristics were then captured in a custom process design kit and used to develop a four-tier compute-in-memory accelerator aimed at large-language-model workloads.[1][2]
What was demonstrated
| Measure | Value | Context |
|---|---|---|
| Fabricated devices | More than 100,000 | Indium-oxide devices produced across the wafer-scale demonstration.Source 1 |
| Wafer size | 200 millimetres | A standard industrially relevant wafer diameter, although not proof of commercial yield.Source 1 |
| Fabricated functional tiers | 3 | Ferroelectric, enhancement-mode and depletion-mode device layers.Source 1Source 2 |
| Accelerator architecture | 4 tiers | A compute-in-memory design created with a custom process design kit.Source 1 |
| Reported speed-up | 1.4× to 2.9× | Benchmark result against two-dimensional baselines for language-model workloads.Source 1 |
The vertical stack gives each tier a different job
| Tier or element | Device role | Why the combination matters |
|---|---|---|
| Tier 1 | Ferroelectric transistors | Provides non-volatile memory that can retain state.Source 2 |
| Tier 2 | Enhancement-mode transistors | Acts as switching and access circuitry.Source 1Source 2 |
| Tier 3 | Depletion-mode transistors | Supports complementary circuit behaviour and cross-tier logic.Source 1Source 2 |
| Tier 4 in the accelerator design | Additional mixed logic and memory organisation | Places computation closer to stored model data.Source 1 |
| Interlayer connections | Vertical vias | Shortens selected paths between functions compared with a flat layout.Source 2 |
The point is to reduce data movement
Large-model inference repeatedly fetches weights, combines them with activations and writes intermediate results. When memory and arithmetic sit far apart, moving bits can cost more than the arithmetic itself. Compute-in-memory architectures try to perform parts of the operation where the data is stored.
Vertical integration adds another lever. Instead of only packing devices more tightly on one plane, designers can put different memory and logic technologies on separate layers. The approach is attractive when a material can be deposited without destroying the circuitry below it and when the resulting devices remain sufficiently uniform across a large wafer.
Manufacturability is the difficult word
The paper reports threshold-voltage standard deviations as low as 0.04 volts and average electron mobility up to 91.6 square centimetres per volt-second, alongside functioning cross-tier circuits. Those measurements address a central concern: a clever vertical device is not useful if variations make a large array unpredictable.[1]
But a research wafer is not a production line. Commercial qualification would have to establish yield across many wafers, endurance, retention, thermal behaviour, packaging, defect tolerance and compatibility with the rest of an advanced manufacturing flow. A process design kit is an important bridge from device physics to circuits; it is not a foundry product announcement.
The achievement is best understood as a demonstration of vertical specialisation. One material system supplied several device behaviours, those behaviours were connected across tiers, and the measurements were made usable to circuit designers. The future chip is not simply smaller. It is organised more like a building in which each floor performs a different part of the computation.
Sources & further reading
- Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers Nature Nanotechnology · 15 Sep 2026 · Accessed 16 Oct 2026
- Building indium oxide transistors in three dimensions Nature Electronics · 14 Oct 2026 · Accessed 16 Oct 2026